During dynamic or in situ memory burn-in, the memory is tested. Typically, a memory burn-in runs for approximately eight to twenty-four hours. In order to test the memory, conventional systems utilize a test sequence which is repeated many times over this period.
For example, some conventional systems use a deterministic data generator to provide predetermined data for testing. In such conventional systems, a simple counter is typically used to generate addresses of the cells to be tested. Consequently, the test sequence is repeated many times. These conventional systems compare the data generated to the data from the memory. If the two do not match, an error has occurred.
The conventional system could also use a read modified write test. The test writes data, reads the data, and writes the complement of the data to the same address. The test then reads the data and moves to the next address. This test determines whether every cell can write to a one or zero and if each address is unique. However, the test does not detect certain fails due to a particular unusual configuration. For example, when a particular bit is set at zero but the adjacent bits are all one, the zero may flip to a one. As a result, such errors will go undetected.
Other conventional systems utilize a pair of linear feedback shift registers ("LFSR") to generate the addresses and the data. A multiple input shift register ("MISR") typically captures a unique signature for each pattern written to the memory. The MISR feeds back two of the data bits to an exclusive or ("XOR"), and uses the XOR as an input to one bit. The MISR also performs an XOR on each of the incoming and outgoing data bits. The MISR, therefore, captures a unique signature for each set of data. At the end of the memory burn-in, the final signature should match an expected signature. If the signatures do not match, an fail has occurred. In order to determine where the fail has occurred, further diagnosis is typically necessary.
A method akin to a binary search may be utilized to determine where the fail occurred. For example, if the signatures do not match at the end of the burn-in, half of the test may be run to determine if the signature correct half way through the burn in. If this signature matches what is expected, then one-fourth of a test is performed. This procedure continues until the fail is found. Thus, in order to determine where the error is, the data must be simulated to know what the MISR should read at the intervening points.
Although conventional systems provide testing in memory burn-in, only a limited number of address patterns are generated. Consequently, unusual patterns which may cause errors are not tested. In a system utilizing a MISR, additional steps are necessary to determine if an error has occurred and which pattern resulted in the error.
Accordingly, what is needed is a system and method for providing memory burn-in having a greater number of test patterns without a significant increase in circuitry. The present invention addresses such a need.